1. Technical Field
The present invention relates to a method for manufacturing a semiconductor device, a semiconductor chip, and a semiconductor wafer.
2. Related Art
Semiconductor chip is generally manufactured by forming a plurality of chip-composing portions, each of which later configures a semiconductor chip (simply referred to as “chip”, hereinafter) on a single semiconductor wafer (simply referred to as “wafer”, hereinafter), and then by cutting (dicing) the wafer along dicing region using a dicer, so as to separate the individual chip-composing portions from each other.
Inter-chip interconnects which connect adjacent ones of the chip-composing portions sequentially with each other, may occasionally be provided, typically for the purpose of inspecting en bloc the plurality of chip-composing portions in a single wafer, in a step preceding the separation of the individual chip-composing portions. Formation of the inter-chip interconnects which connect the chip-composing portions are described in Japanese Laid-Open Patent Publication Nos. 2000-286316, H08-181330, and H05-29413, for example.
The inter-chip interconnects between adjacent ones of the chip-composing portions are cut by dicing using a dicer. In the process of dicing, chipping may occur in the wafer.
Japanese Laid-Open Patent Publication No. 2004-235357 discloses a technique of arranging rectangular dummy patterns arrayed in a lattice pattern over the entire portion of the dicing region, for the purpose of suppressing spreading of the chipping in the wafer in the process of dicing, although the inter-chip interconnects are not mentioned. This publication relates to the dummy patterns disposed for the purpose of improving in-plane uniformity of CMP (chemical mechanical polishing). The dummy pattern may, therefore, be supposedly composed of copper (Cu).